[virt-tools-list] [virt-manager PATCH] cli: Add --clock timer[0-9]*.catchup options

athina.plaskasoviti at gmail.com athina.plaskasoviti at gmail.com
Sat Aug 17 16:10:03 UTC 2019


From: Athina Plaskasoviti <athina.plaskasoviti at gmail.com>

Added:
-timer[0-9]*.catchup.threshold
-timer[0-9]*.catchup.slew
-timer[0-9]*.catchup.limit

Catchup attributes need timer with assigned tickpolicy=catchup.

XML Mapping:

<clock>
  ...
  <catchup threshold="X" slew="X" limit="X"/>
  ...
</clock>

Signed-off-by: Athina Plaskasoviti <athina.plaskasoviti at gmail.com>
---
 .../compare/virt-install-singleton-config-2.xml             | 6 ++++++
 tests/clitest.py                                            | 2 +-
 virtinst/cli.py                                             | 6 ++++++
 virtinst/domain/clock.py                                    | 3 +++
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
index 0d202de8..c301e256 100644
--- a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
+++ b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
@@ -156,6 +156,9 @@
     <timer name="rtc" track="wall"/>
     <timer name="tsc" frequency="10"/>
     <timer name="tsc" mode="emulate"/>
+    <timer name="rtc" tickpolicy="catchup">
+      <catchup threshold="123" slew="120" limit="10000"/>
+    </timer>
   </clock>
   <on_poweroff>destroy</on_poweroff>
   <on_reboot>destroy</on_reboot>
@@ -380,6 +383,9 @@
     <timer name="rtc" track="wall"/>
     <timer name="tsc" frequency="10"/>
     <timer name="tsc" mode="emulate"/>
+    <timer name="rtc" tickpolicy="catchup">
+      <catchup threshold="123" slew="120" limit="10000"/>
+    </timer>
   </clock>
   <on_poweroff>destroy</on_poweroff>
   <on_reboot>restart</on_reboot>
diff --git a/tests/clitest.py b/tests/clitest.py
index 6818612d..43b8f4e2 100644
--- a/tests/clitest.py
+++ b/tests/clitest.py
@@ -526,7 +526,7 @@ memnode0.cellid=1,memnode0.mode=strict,memnode0.nodeset=2
 --blkiotune weight=100,device_path=/home/test/1.img,device_weight=200
 --memorybacking size=1,unit='G',nodeset=0,1,nosharepages=yes,locked=yes,discard=yes,allocation.mode=immediate,access_mode=shared,source_type=file,hugepages.page.size=12,hugepages.page1.size=1234,hugepages.page1.unit=MB,hugepages.page1.nodeset=2
 --features acpi=off,eoi=on,privnet=on,hyperv_synic=on,hyperv_reset=on,hyperv_spinlocks=on,hyperv_spinlocks_retries=5678,vmport=off,pmu=off,vmcoreinfo=on,kvm_hidden=off,hyperv_vapic=on
---clock offset=utc,hpet_present=no,rtc_tickpolicy=merge,timer2.name=hypervclock,timer3.name=pit,timer1.present=yes,timer3.tickpolicy=delay,timer2.present=no,timer4.name=rtc,timer5.name=tsc,timer6.name=tsc,timer4.track=wall,timer5.frequency=10,timer6.mode=emulate
+--clock offset=utc,hpet_present=no,rtc_tickpolicy=merge,timer2.name=hypervclock,timer3.name=pit,timer1.present=yes,timer3.tickpolicy=delay,timer2.present=no,timer4.name=rtc,timer5.name=tsc,timer6.name=tsc,timer4.track=wall,timer5.frequency=10,timer6.mode=emulate,timer7.name=rtc,timer7.tickpolicy=catchup,timer7.catchup.threshold=123,timer7.catchup.slew=120,timer7.catchup.limit=10000
 --sysinfo type=smbios,bios_vendor="Acme LLC",bios_version=1.2.3,bios_date=01/01/1970,bios_release=10.22
 --sysinfo type=smbios,system_manufacturer="Acme Inc.",system_product=Computer,system_version=3.2.1,system_serial=123456789,system_uuid=00000000-1111-2222-3333-444444444444,system_sku=abc-123,system_family=Server
 --sysinfo type=smbios,baseBoard_manufacturer="Acme Corp.",baseBoard_product=Motherboard,baseBoard_version=A01,baseBoard_serial=1234-5678,baseBoard_asset=Tag,baseBoard_location=Chassis
diff --git a/virtinst/cli.py b/virtinst/cli.py
index 0affe513..97145e59 100644
--- a/virtinst/cli.py
+++ b/virtinst/cli.py
@@ -2546,6 +2546,12 @@ class ParserClock(VirtCLIParser):
                     find_inst_cb=cls.timer_find_inst_cb)
         cls.add_arg("timer[0-9]*.frequency", "frequency",
                     find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.catchup.threshold", "threshold",
+                    find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.catchup.slew", "slew",
+                    find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.catchup.limit", "limit",
+                    find_inst_cb=cls.timer_find_inst_cb)
 
 
 ################
diff --git a/virtinst/domain/clock.py b/virtinst/domain/clock.py
index 1647ab78..831839d6 100644
--- a/virtinst/domain/clock.py
+++ b/virtinst/domain/clock.py
@@ -16,6 +16,9 @@ class _ClockTimer(XMLBuilder):
     track = XMLProperty("./@track")
     mode = XMLProperty("./@mode")
     frequency = XMLProperty("./@frequency", is_int=True)
+    threshold = XMLProperty("./catchup/@threshold", is_int=True)
+    slew = XMLProperty("./catchup/@slew", is_int=True)
+    limit = XMLProperty("./catchup/@limit", is_int=True)
 
 
 class DomainClock(XMLBuilder):
-- 
2.21.0




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