[virt-tools-list] [virt-manager PATCH] cli: Add --clock timer[0-9]*.track, timer[0-9]*.mode, timer[0-9]*.frequency options

[Athina Plaskasoviti]

XML Mapping:

<clock>
...
  <timer track="X" mode="X" frequency="X"/>
...
</clock>

Signed-off-by: Athina Plaskasoviti <athina.plaskasoviti at gmail.com>
---
 .../compare/virt-install-singleton-config-2.xml             | 6 ++++++
 tests/clitest.py                                            | 2 +-
 virtinst/cli.py                                             | 6 ++++++
 virtinst/domain/clock.py                                    | 3 +++
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
index 9d5907c5..cf03abec 100644
--- a/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
+++ b/tests/cli-test-xml/compare/virt-install-singleton-config-2.xml
@@ -150,6 +150,9 @@
     <timer name="hpet" present="yes"/>
     <timer name="hypervclock" present="no"/>
     <timer name="pit" tickpolicy="delay"/>
+    <timer name="rtc" track="wall"/>
+    <timer name="tsc" frequency="10"/>
+    <timer name="tsc" mode="emulate"/>
   </clock>
   <on_poweroff>destroy</on_poweroff>
   <on_reboot>destroy</on_reboot>
@@ -368,6 +371,9 @@
     <timer name="hpet" present="yes"/>
     <timer name="hypervclock" present="no"/>
     <timer name="pit" tickpolicy="delay"/>
+    <timer name="rtc" track="wall"/>
+    <timer name="tsc" frequency="10"/>
+    <timer name="tsc" mode="emulate"/>
   </clock>
   <on_poweroff>destroy</on_poweroff>
   <on_reboot>restart</on_reboot>
diff --git a/tests/clitest.py b/tests/clitest.py
index 1f7730fb..7f7ad37a 100644
--- a/tests/clitest.py
+++ b/tests/clitest.py
@@ -526,7 +526,7 @@ memnode0.cellid=1,memnode0.mode=strict,memnode0.nodeset=2
 --blkiotune weight=100,device_path=/home/test/1.img,device_weight=200
 --memorybacking size=1,unit='G',nodeset=0,1,nosharepages=yes,locked=yes,discard=yes,allocation.mode=immediate,access_mode=shared,source_type=file,hugepages.page.size=12,hugepages.page1.size=1234,hugepages.page1.unit=MB,hugepages.page1.nodeset=2
 --features acpi=off,eoi=on,privnet=on,hyperv_synic=on,hyperv_reset=on,hyperv_spinlocks=on,hyperv_spinlocks_retries=5678,vmport=off,pmu=off,vmcoreinfo=on,kvm_hidden=off,hyperv_vapic=on
---clock offset=utc,hpet_present=no,rtc_tickpolicy=merge,timer2.name=hypervclock,timer3.name=pit,timer1.present=yes,timer3.tickpolicy=delay,timer2.present=no
+--clock offset=utc,hpet_present=no,rtc_tickpolicy=merge,timer2.name=hypervclock,timer3.name=pit,timer1.present=yes,timer3.tickpolicy=delay,timer2.present=no,timer4.name=rtc,timer5.name=tsc,timer6.name=tsc,timer4.track=wall,timer5.frequency=10,timer6.mode=emulate
 --sysinfo type=smbios,bios_vendor="Acme LLC",bios_version=1.2.3,bios_date=01/01/1970,bios_release=10.22
 --sysinfo type=smbios,system_manufacturer="Acme Inc.",system_product=Computer,system_version=3.2.1,system_serial=123456789,system_uuid=00000000-1111-2222-3333-444444444444,system_sku=abc-123,system_family=Server
 --sysinfo type=smbios,baseBoard_manufacturer="Acme Corp.",baseBoard_product=Motherboard,baseBoard_version=A01,baseBoard_serial=1234-5678,baseBoard_asset=Tag,baseBoard_location=Chassis
diff --git a/virtinst/cli.py b/virtinst/cli.py
index 2ca286be..bed83c73 100644
--- a/virtinst/cli.py
+++ b/virtinst/cli.py
@@ -2536,6 +2536,12 @@ class ParserClock(VirtCLIParser):
                     find_inst_cb=cls.timer_find_inst_cb)
         cls.add_arg("timer[0-9]*.tickpolicy", "tickpolicy",
                     find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.track", "track",
+                    find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.mode", "mode",
+                    find_inst_cb=cls.timer_find_inst_cb)
+        cls.add_arg("timer[0-9]*.frequency", "frequency",
+                    find_inst_cb=cls.timer_find_inst_cb)
 
 
 ################
diff --git a/virtinst/domain/clock.py b/virtinst/domain/clock.py
index f61a51ad..1647ab78 100644
--- a/virtinst/domain/clock.py
+++ b/virtinst/domain/clock.py
@@ -13,6 +13,9 @@ class _ClockTimer(XMLBuilder):
     name = XMLProperty("./@name")
     present = XMLProperty("./@present", is_yesno=True)
     tickpolicy = XMLProperty("./@tickpolicy")
+    track = XMLProperty("./@track")
+    mode = XMLProperty("./@mode")
+    frequency = XMLProperty("./@frequency", is_int=True)
 
 
 class DomainClock(XMLBuilder):
-- 
2.20.1